Field of the Invention
This invention relates generally to a variable baud rate data communication system and more particularly to a data interface between a display or date pager and a printer through a single unidirectional port.
Whenever it is necessary for communication to take place between two pieces of digital equipment, it is normally necessary to provide some sort of synchronization between the two pieces of equipment so that the receiving equipment knows when to look for valid data. In some such systems, a clock signal is recovered from the transmitted data and used to clock the receipt of data by the receiving equipment. In other such systems a separate clock signal may be transmitted from the transmitting equipment to the receiving equipment for similar purposes. Still other systems may utilize multiple sampling of each bit by the receiving equipment in order to asynchronously detect the data being transmitted.
Each of these systems has its drawbacks. For example, when the clock signal must be derived from the encoded data, complex decoding circuitry is necessary in the receiving equipment in order to accomplish this. In addition, wide bandwidth circuitry may also be necessary depending on the data rate. When a separate clock line is used, separate hardware interconnections for the clock line are necessary. This may be prohibitive when dealing with miniaturized equipment such as paging receivers. In asynchronous multiple sample per bit systems, complex circuitry is also necessary to assure freedom from or minimization of errors.
In each of these techniques it is also desirable if not necessary for the receiving equipment to know the approximate frequency of transmission of data from the transmitting equipment. The present invention circumvents these problems by providing a system of communications between a pager and a printer or other peripheral which may operate at a truly variable baud rate (up to the maximum hardware limitations of the receiving and transmitting circuitry). Only one interconnection line is necessary and encoding and decoding circuitry remain simple.